Ãàâðèëîâ Ñåðãåé Âèòàëüåâè÷ |
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˜˜˜˜˜ ˜˜˜˜˜˜˜ ˜˜˜˜˜˜˜˜˜
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Ìîíîãðàôèè: |
 Ãàâðèëîâ Ñ.Â., Ãëåáîâ À.Ë., Ñòåìïêîâñêèé À.Ë. Ìåòîäû ëîãè÷åñêîãî è ëîãèêî-âðåìåííîãî àíàëèçà öèôðîâûõ ÊÌÎÏ ÑÁÈÑ // M.: Íàóêà, 2007, 220c. |
| Ãàâðèëîâ Ñ.Â. Ìåòîäû àíàëèçà ëîãè÷åñêèõ êîððåëÿöèé äëÿ ÑÀÏÐ öèôðîâûõ ÊÌÎÏ ÑÁÈÑ // Ì.: Òåõíîñôåðà, 2011. 136 c. |
Èçáðàííûå ðàáîòû: |
 S. Gavrilov, A. Glebov, S. Rusakov, D. Blaauw, L. Jones, G. Vijayan. Fast Power loss calculation for digital static CMOS circuits // Proc. Of European Design and Test Conference (ED&TC), Paris, France, 1997, P.411. |
| S. Gavrilov, A. Glebov, S. Pullela, S. Moore, G. Vijayan, A. Dharchoundhury, R. Panda, D. Blaauw. Library-less synthesis for static CMOS combinational logic circuits // Proc. of IEEE/ACM intern. Conference on computer aided design (ICCAD), San Jose, CA, 1997, P.658. |
| A. Glebov, S. Gavrilov, D. Blaauw, S .Sirichotiyakul, C. Oh, V. Zolotov. False-Noise Analysis using Logic Implications // Proc. of IEEE/ACM intern. Conference on computer aided design (ICCAD), San Jose, CA, 2001, P.515. |
| A. Glebov, S. Gavrilov, D. Blaauw, V. Zolotov, R. Panda, C. Oh. False-Noise Analysis Using Resolution Method // Intern. Symp. on Quality Electronic Design (ISQED), San Jose, CA, 2002, P.437. |
A. Glebov, S. Gavrilov, D. Blaauw, V. Zolotov. False-noise analysis using logic implications // ACM Transactions on Design Automation of Electronic Systems (TODAES), 2002, v.7, ¹3, P.474-498. 
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| Ñ.Â. Ãàâðèëîâ, À.Ë. Ãëåáîâ, À.Ë. Ñòåìïêîâñêèé. Àíàëèç ïîìåõîóñòîé÷èâîñòè öèôðîâûõ ñõåì íà îñíîâå ëîãè÷åñêèõ èìïëèêàöèé // Èçâåñòèÿ ÂÓÇîâ, Ýëåêòðîíèêà, 2002, ¹5, C.60. |
| Ñ.Â. Ãàâðèëîâ, À.Ë. Ãëåáîâ, À.Ë. Ñòåìïêîâñêèé. Áûñòðûé àëãîðèòì ðàñ÷åòà ìîùíîñòè â öèôðîâûõ ÊÌÎÏ ñõåìàõ // Ýëåêòðîíèêà ÍÒÁ, 2002, ¹6, C.40. |
| Ñ.Â. Ãàâðèëîâ, À.Ë. Ãëåáîâ, À.Ë. Ñòåìïêîâñêèé. Ñòðóêòóðíàÿ îïòèìèçàöèÿ öèôðîâûõ ÊÌÎÏ ñõåì // Èíôîðìàöèîííûå òåõíîëîãèè è âû÷èñëèòåëüíûå ñèñòåìû, 2002, ¹4., C.40-47 |
| D.Blaauw,S.Gavrilov,A.Glebov,Y.Egorov,D.Nadezchin,etc. SOI transistor model for fast transient simulation // In Proc. of ICCAD, 2003, P.120-127.
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| S.Gavrilov, A.Glebov, V.Zolotov, etc. False-Noise Analysis for Domino Circuits // In Proc. of DATE, Paris Feb. 2004, P.784-789.
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| S.Gavrilov,A.Glebov,R.Soloviev,M.Becer,etc. Delay Noise Pessimism Reduction by Logic Correlations // In Proc. of ICCAD, 2004, P. 160-167. |
| À.Ë.Ñòåìïêîâñêèé, Ñ.Â.Ãàâðèëîâ,À.Ë.Ãëåáîâ.Àíàëèç ôàòàëüíûõ ïîìåõ â öèôðîâûõ ñõåìàõ íà îñíîâå ìåòîäà ðåçîëþöèé // Ýëåêòðîíèêà,Èçâåñòèÿ ÂÓÇîâ, N6, 2004, C.64-72. |
| À.Ë.Ñòåìïêîâñêèé, Ñ.Â.Ãàâðèëîâ,À.Ë.Ãëåáîâ. Àíàëèç ïîìåõîóñòîé÷èâîñòè öèôðîâûõ ñõåì òèïà "äîìèíî // Èíôîðìàöèîííûå òåõíîëîãèè è âû÷èñëèòåëüíûå ñèñòåìû, ¹10, 2004, C.2-7. |
| Ñ.Â.Ãàâðèëîâ, Ð.À.Ñîëîâüåâ, À.Ë.Ãëåáîâ. Àíàëèç ïîìåõ âëèÿþùèõ íà çàäåðæêó ïðîõîæäåíèÿ ñèãíàëà â öèôðîâûõ ÑÁÈÑ, íà îñíîâå ëîãè÷åñêèõ îãðàíè÷åíèé // Ýëåêòðîíèêà, Èçâåñòèÿ ÂÓÇîâ, 2005. - ¹6, Ñ. 61-67. |
| Ãàâðèëîâ Ñ.Â., Ãëåáîâ À.Ë., Ñòåìïêîâñêèé À.Ë. Ñòàòèñòè÷åñêèé ïîäõîä ê âðåìåííîìó àíàëèçó öèôðîâûõ ñõåì // Èçâåñòèÿ ÂÓÇîâ. Ýëåêòðîíèêà, 2006, ¹ 5, Ñ.99-106. |
| Ãàâðèëîâ Ñ.Â., Ãëåáîâ À.Ë., Ñòåìïêîâñêèé À.Ë. Ìåòîäû ïîâûøåíèÿ ýôôåêòèâíîñòè âðåìåííîãî àíàëèçà ÑÁÈÑ // Èíôîðìàöèîííûå òåõíîëîãèè, 2006, ¹12, Ñ.2-12. |
| Ãàâðèëîâ Ñ.Â., Ãëåáîâ À.Ë., Ñîëîâüåâ Ð.À. Îáíàðóæåíèå ëîæíûõ ïóòåé â öèôðîâîé ñõåìå íà îñíîâå ëîãè÷åñêèõ èìïëèêàöèé // Èçâåñòèÿ ÂÓÇîâ, Ýëåêòðîíèêà, 2007, ¹2, Ñ.78-84. |
| Ãàâðèëîâ Ñ.Â., Ãëåáîâ À.Ë., Åãîðîâ Þ.Á., Ñòåìïêîâñêèé À.Ë. Ìåòîäû ìíîãîóðîâíåâîãî àíàëèçà áûñòðîäåéñòâèÿ öèôðîâûõ ÊÌÎÏ ÑÁÈÑ // Èçâåñòèÿ ÂÓÇîâ. Ýëåêòðîíèêà. – 2007. - ¹ 4. – Ñ. 28-36. |
| Savithri Sundareswaran, Sergey Gavrilov, Roman Soloviev, Rajendran Panda A Timing Methodology Considering Within-Die Clock Skew Variations // IEEE International SOC conference, 2008, Newport Beach, CA, P.351-356.
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| À.Ë. Ñòåìïêîâñêèé, Ñ.Â. Ãàâðèëîâ, Ý.Ð. Êàãðàìàíÿí Ìåòîäû ëîãèêî-âðåìåííîãî àíàëèçà çàêàçíûõ áëîêîâ ÑÁÈÑ // Èçâåñòèÿ ÂÓÇîâ. Ýëåêòðîíèêà. 2008. ¹5. Ñ.41-50. |
| Ãàâðèëîâ Ñ.Â., Ãóäêîâà Î.Í., Êàãðàìàíÿí Ý.Ð. Àíàëèç íàäåæíîñòè ôóíêöèîíèðîâàíèÿ öèôðîâûõ ÊÌÎÏ ÑÁÈÑ ñ ó÷åòîì ýôôåêòîâ äåãðàäàöèè òðàíçèñòîðîâ. // Èçâåñòèÿ ÂÓÇîâ. Ýëåêòðîíèêà. 2008. ¹6. Ñ.30-40. |
| Ñ.Â. Ãàâðèëîâ, Ý.Ð. Êàãðàìàíÿí, Ë.Ñ. Õîäîø Òåíäåíöèè ðàçâèòèÿ ìîäåëåé áèáëèîòå÷íûõ ýëåìåíòîâ äëÿ ñòàòè÷åñêîãî âðåìåííîãî àíàëèçà öèôðîâûõ ÑÁÈÑ // Èíôîðìàöèîííûå òåõíîëîãèè. 2009, ¹ 3, C.20-24. |
| À.Ë.Ñòåìïêîâñêèé, À.Ë. Ãëåáîâ, Ñ.Â. Ãàâðèëîâ, Î.Í.Ãóäêîâà Âåðîÿòíîñòè íàïðÿæåííîãî ñîñòîÿíèÿ òðàíçèñòîðîâ äëÿ âðåìåííîãî àíàëèçà ñ ó÷åòîì ýëåêòðîòåìïåðàòóðíîé íåñòàáèëüíîñòè // Èíôîðìàöèîííûå òåõíîëîãèè. 2009, ¹7, Ñ.32–38 |
| Alexander Stempkovsky, Alexey Glebov, Sergey Gavrilov. Calculation of Stress Probability for NBTI-Aware Timing Analysis // Proc. of ISQED, 2009, P.714-718.
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| Ãàâðèëîâ Ñ.Â., Ãóäêîâà Î.Í., Åãîðîâ Þ.Á. Ìåòîäû óñêîðåííîé õàðàêòåðèçàöèè áèáëèîòåê ýëåìåíòîâ ÑÁÈÑ ñ êîíòðîëåì çàäàííîé òî÷íîñòè // Èçâåñòèÿ ÂÓÇîâ. Ýëåêòðîíèêà. 2010. ¹ 3. Ñ. 51-59. |
| Ãàâðèëîâ Ñ.Â., Ãóäêîâà Î.Í., Ùåëîêîâ À.Í. Àíàëèç äåãðàäàöèè ïàðàìåòðîâ òðàíçèñòîðîâ âî âðåìåíè íà ëîãè÷åñêîì óðîâíå // Èçâåñòèÿ ÞÔÓ. Òåõíè÷åñêèå íàóêè. 2011. ¹7. Ñ.188-197. |
| S. V. Gavrilov, O. N. Gudkova and Yu. B. Egorov. Methods of accelerated characterization of VLSI cell libraries with prescribed accuracy control // Russian Microelectronics, Vol.40, N7, 2011, P.476-482. |
| Ñ.Â. Ãàâðèëîâ, Î.Í. Ãóäêîâà, À.Ë. Ñòåìïêîâñêèé. Àíàëèç áûñòðîäåéñòâèÿ íàíîìåòðîâûõ ñëîæíî-ôóíêöèîíàëüíûõ áëîêîâ íà îñíîâå èíòåðâàëüíîãî ìîäåëèðîâàíèÿ. // Èçâåñòèÿ ÂÓÇîâ. Ýëåêòðîíèêà. – 2012. - ¹ 4. – C. 40-49 |
| Ñ.Â. Ãàâðèëîâ, Ã.À. Ïèðþòèíà, À.Í. Ùåëîêîâ. Ìåòîä èíòåðâàëüíûõ îöåíîê çàäåðæåê è âûõîäíûõ ôðîíòîâ áèáëèîòå÷íûõ ýëåìåíòîâ íàíîìåòðîâûõ ÊÌÎÏ-ñõåì. // Èçâåñòèÿ ÞÔÓ. Òåõíè÷åñêèå íàóêè. – 2012. - ¹7 (132). - Ñ. 70-76. |
| Ñ.Â. Ãàâðèëîâ, Î.Í. Ãóäêîâà, À.Í. Ùåëîêîâ. Ëîãèêî-âðåìåííîé àíàëèç íàíîìåòðîâûõ ñõåì íà îñíîâå èíòåðâàëüíîãî ïîäõîäà. // Èçâåñòèÿ ÞÔÓ. Òåõíè÷åñêèå íàóêè. – 2012. - ¹7 (132). - Ñ. 85-91. |
| S.V. Gavrilov, O.N. Gudkova, A.L. Stempkovskiy. The Analysis of the Performance of Nanometer IP-blocks Based on Interval Simulation. // Russian Microelectronics, Vol.42, N7, 2013, P. 396–402. © Pleiades Publishing, Ltd., 2013. |
| Sergey Gavrilov, Olga Gudkova, Roman Soloviev. Timing Analysis for Complex Digital Gates and Circuits Accounting for Transistor Degradation // Proceedings of SEUA. Series “Information technologies, Electronics, Radio engineering”. Issue 16, N1, 2013, P.84-93 |
| Ãàâðèëîâ Ñ.Â., Ðûæîâà Ä.È., Ñòåìïêîâñêèé À.Ë. Ïðîáëåìà àíàëèçà ïèêîâîãî òîêà ïðè ïðîåêòèðîâàíèè ñâåðõáîëüøèõ èíòåãðàëüíûõ ñõåì íà ëîãè÷åñêîì óðîâíå è ñîâðåìåííûå ìåòîäû åå ðåøåíèÿ // Èíôîðìàöèîííûå òåõíîëîãèè. – 2014. ¹ 6. Ñ. 58—63. |
| Ãàâðèëîâ Ñ.Â., Èâàíîâà Ã.À., Ìàíóêÿí À.À. Íîâûå ïðîáëåìû ëîãèêî-òîïîëîãè÷åñêîãî ñèíòåçà çàêàçíûõ ñëîæíî-ôóíêöèîíàëüíûõ áëîêîâ è ìåòîäû èõ ðåøåíèÿ // Èíôîðìàöèîííûå òåõíîëîãèè. – 2014. ¹ 8. Ñ. 44—50 |
| Ãàâðèëîâ Ñ.Â., Ðûæîâà Ä.È., Ñòåìïêîâñêèé À.Ë. Ìåòîäû ïîâûøåíèÿ òî÷íîñòè îöåíêè ïèêîâîãî òîêà íà ëîãè÷åñêîì óðîâíå íà îñíîâå àíàëèçà ëîãè÷åñêèõ êîððåëÿöèé // Èçâåñòèÿ ÞÔÓ. Òåõíè÷åñêèå íàóêè. – 2014. ¹ 7, C. 66-75 |
| Ãàâðèëîâ Ñ.Â., Èâàíîâà Ã.À., Ñòåìïêîâñêèé À.Ë. Òåîðåòèêî-ãðàôîâàÿ ìîäåëü ñëîæíî-ôóíêöèîíàëüíûõ áëîêîâ äëÿ ÊÌÎÏ òåõíîëîãèé ñ òðåõìåðíîé ñòðóêòóðîé òðàíçèñòîðà // Èçâåñòèÿ ÞÔÓ. Òåõíè÷åñêèå íàóêè. – 2014. ¹ 7, C. 58-66. |
| Sergey Gavrilov, Galina Ivanova, Pavel Volobuev, Aram Manukyan. Methods of logical synthesis for library elements and blocks with regular layout structure // 2015 IEEE 35th International Conference on Electronics and Nanotechnology (ELNANO-2015), 2015, P. 138-141. |
| Ãàâðèëîâ Ñ.Â., Ðûæîâà Ä.È. Àëãîðèòì îöåíêè ïèêîâîãî òîêà íà ëîãè÷åñêîì óðîâíå ïðîåêòèðîâàíèÿ íà îñíîâå àíàëèçà ðàñïðîñòðàíåíèÿ ëîãè÷åñêèõ êîððåëÿöèé â ñõåìå // Âåñòíèê Ðÿçàíñêîãî ãîñóäàðñòâåííîãî ðàäèîòåõíè÷åñêîãî óíèâåðñèòåòà. 2015. ¹2 (Âûïóñê 52). Ñ. 56-64. |
| Gavrilov S., Ivanova G. Simultaneous Logic and Layout Synthesis for Fin-fet Based Elements with Regular Layout in Ðolysilicon and Diffusion // Proceedings of IEEE East-West Design & Test Symposium (EWDTS’2015), 2015, P. 264-267. |
| Ãàâðèëîâ Ñ.Â., Èâàíîâà Ã.À. Àíàëèç áûñòðîäåéñòâèÿ ñëîæíûõ öèôðîâûõ ñõåì ñ ó÷åòîì íåîïðåäåëåííîñòè òåõíîëîãè÷åñêèõ è ñõåìíûõ ïàðàìåòðîâ // Âåñòíèê Ðÿçàíñêîãî ãîñóäàðñòâåííîãî ðàäèîòåõíè÷åñêîãî óíèâåðñèòåòà. 2015. (Âûïóñê 53). Ñ. 29-35. |
| Ãàâðèëîâ Ñ.Â., Èâàíîâà Ã.À., Ñîëîâüåâ À.Í., Ñòåìïêîâñêèé À.Ë. Îïòèìèçàöèÿ ñõåì êîäèðîâàíèÿ íà îñíîâå âûáîðà âàðèàíòà êîììóòàöèé ñ ó÷åòîì ëîãè÷åñêèõ êîððåëÿöèé ìåæäó âûõîäàìè êîìáèíàöèîííîé ñõåìû // Èçâåñòèÿ ÞÔÓ. Òåõíè÷åñêèå íàóêè. – 2015. ¹6(167). C. 255-262. |
| Âîëîáóåâ Ï.Ñ., Ãàâðèëîâ Ñ.Â., Ðûæîâà Ä.È., Ñòåìïêîâñêèé À.Ë. Îïðåäåëåíèå ðàçìåðîâ êëþ÷åâûõ òðàíçèñòîðîâ â íèçêîìîùíûõ ÊÌÎÏ ñõåìàõ äëÿ ìåòîäà îòêëþ÷åíèÿ ïèòàíèÿ ñ êîíòðîëåì áûñòðîäåéñòâèÿ // Èçâåñòèÿ ÞÔÓ. Òåõíè÷åñêèå íàóêè. – 2015. ¹6(167). C. 106-115. |
| Ãàâðèëîâ Ñ.Â., Èâàíîâà Ã.À., Ðûæîâà Ä.È., Ñîëîâüåâ À.Í., Ñòåìïêîâñêèé À.Ë. Ìåòîäû ñèíòåçà ïîìåõîçàùèùåííûõ êîìáèíàöèîííûõ áëîêîâ // Èíôîðìàöèîííûå òåõíîëîãèè. 2015, Ò. 21, ¹11, Ñ. 821-826. |
| A.L. Stempkovsky, S.V. Gavrilov, I.V. Matyushkin, and G.S. Teplov. On the Issue of Application of Cellular Automata and Neural Networks Methods in VLSI Design) // Optical Memory and Neural Networks. 2016. Vol. 25. No. 2. Pp. 72–78. |
| Ãàâðèëîâ Ñ.Â., Ðûæîâà Ä.È. Ìàðøðóò ëîãèêî-òîïîëîãè÷åñêîãî ñèíòåçà êîìáèíàöèîííûõ ñõåì äëÿ ÊÌÎÏ òåõíîëîãèé ñ òðåõìåðíûì çàòâîðîì òðàíçèñòîðà // Èçâåñòèÿ ÞÔÓ. Òåõíè÷åñêèå íàóêè. – 2016. ¹6 (179). C. 131-141. |
| Ãàâðèëîâ Ñ.Â., Æåëåçíèêîâ Ä.À., Õâàòîâ Â.Ì. Ñîâìåñòíîå ðåøåíèå çàäà÷ òðàññèðîâêè ìåæñîåäèíåíèé ñ ðåñèíòåçîì äëÿ ðåêîíôèãóðèðóåìûõ ñèñòåì íà êðèñòàëëå // Èçâåñòèÿ ÂÓÇîâ. Ýëåêòðîíèêà. – 2017. – Ò. 22. – ¹ 3. – Ñ. 266-275. |
| S. V. Gavrilov, S. I. Gurov, T. D. Zhukova, V. S. Rukhlov, D. I. Ryzhova, and D. V. Tel’pukhov. Methods to Increase Fault Tolerance of Combinational Integrated Microcircuits by Redundancy Coding // Computational Mathematics and Modeling, 2017, Vol. 28, No. 3. Pp. 400 – 406. |
| Gavrilov S.V., Matyushkin I.V, Stempkovsky A.L. Computability via Cellular Automata // Scientific and Technical Information Processing. – 2017. V.44, ¹5, Pp. 1-15. |
| Ãàâðèëîâ Ñ.Â., Èâàíîâà Ã.À., Ëÿëèíñêàÿ Î.Â. Ïðîãðàììà äëÿ àíàëèçà áûñòðîäåéñòâèÿ èíòåãðàëüíûõ ñõåì ñ ó÷åòîì âàðèàöèé ñõåìíûõ ïàðàìåòðîâ // Ñâèäåòåëüñòâî î ãîñóäàðñòâåííîé ðåãèñòðàöèè ïðîãðàììû äëÿ ÝÂÌ ¹ 2018610141 îò 09.01.2018. |
| Ãàâðèëîâ Ñ.Â., Æåëåçíèêîâ Ä.À., Çàïëåòèíà Ì.A., Õâàòîâ Â.Ì., ×î÷àåâ Ð.Æ., Ýííñ Â.È., Ìàðøðóò òîïîëîãè÷åñêîãî ñèíòåçà äëÿ ðåêîíôèãóðèðóåìûõ ñèñòåì íà êðèñòàëëå ñïåöèàëüíîãî íàçíà÷åíèÿ // Ìèêðîýëåêòðîíèêà, 2019, òîì 48, ¹ 3, C. 211–223. DOI:10.1134/s0544126919030050 |
| Gavrilov S.V., Zheleznikov D.A., Zapletina M.A., Khvatov V.M., Chochaev R.Z., Enns V.I. Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip // Russian Microelectronics. 2019. 48(3), P. 176-186. DOI:10.1134/s1063739719030053 |
| Khvatov V.M., Zheleznikov D.A., Garbulina T.V., Gavrilov S.V. Post-Route Performance Estimation Method for Reconfigurable System-on-a-Chip // 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), Moscow, 2020, pp. 1804-1808. DOI: 10.1109/EIConRus49466.2020.9039262 |
| ×î÷àåâ Ð.Æ., Æåëåçíèêîâ Ä.A., Èâàíîâà Ã.À., Ãàâðèëîâ Ñ.Â, Ýííñ Â.È. Ìîäåëè è ìåòîäû àíàëèçà ñòðóêòóðû êîììóòàöèîííûõ ðåñóðñîâ ÏËÈÑ // Èçâåñòèÿ âóçîâ. Ýëåêòðîíèêà. 2020. Ò. 25. ¹ 5. Ñ. 410–422. DOI: 10.24151/1561-5405-2020-25-5-410-422 |
| Enns V.I, Gavrilov S.V., Zapletina M.A. Set Based Theoretical Approach to the Representation of Routing Stage in the Design Flow for the Heterogeneous FPGAs and Reconfigurable SoCs // Russian Microelectronics, 2021, Vol. 50, No. 6, pp. 463-470. DOI: 10.1134/S1063739722010061 |
| 352. Zapletina M.A., Gavrilov S.V. Pathfinder Algorithm Modification for the FPGA Interconnect Routing Stage // Russian Microelectronics Vol. 51, No.7, 2022 |
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